Efficient VLSI implementation of modulo (2/sup n//spl plusmn/1) addition and multiplication

R. Zimmermann
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引用次数: 302

Abstract

New VLSI circuit architectures for addition and multiplication modulo (2/sup n/-1) and (2/sup n/+1) are proposed that allow the implementation of highly efficient combinational and pipelined circuits for modular arithmetic. It is shown that the parallel-prefix adder architecture is well suited to realize fast end-around-carry adders used for modulo addition. Existing modulo multiplier architectures are improved for higher speed and regularity. These allow the use of common multiplier speed-up techniques like Wallace-tree addition and Booth recoding, resulting in the fastest known modulo multipliers. Finally, a high-performance modulo multiplier-adder for the IDEA block cipher is presented. The resulting circuits are compared qualitatively and quantitatively, i.e., in a standard-cell technology, with existing solutions and ordinary integer adders and multipliers.
高效VLSI实现模(2/sup n//spl plusmn/1)加法和乘法
提出了用于加法和乘法模(2/sup n/-1)和(2/sup n/+1)的新型VLSI电路结构,允许实现高效的组合和流水线电路用于模块化算法。结果表明,并行前缀加法器结构非常适合于实现用于模加法的快速绕端进位加法器。现有的模乘法器架构改进了更高的速度和规律性。这允许使用常见的乘法器加速技术,如华莱士树加法和布斯重编码,从而产生已知最快的模乘法器。最后,提出了一种用于IDEA分组密码的高性能模乘加器。所得到的电路在定性和定量上进行比较,即在标准单元技术中,与现有的解决方案和普通的整数加法器和乘法器进行比较。
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