Design of Low Power SAR ADC for ECG Using 45nm CMOS Technology

Silpakesav Velagaleti, Nayanathara K.S., Madhavi B.K
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引用次数: 4

Abstract

Design of a low power Successive Approximation Register Analog to Digital Converter (SAR ADC) in 45nm CMOS Technology for biopotential acquisition systems is presented. It is designed by using a high threshold voltage (Vt) cell to reduce power dissipation. A 10-bit SAR ADC is designed and compared with the low resolution SAR ADC and normal threshold voltage (Vt) ADC with respect to power and delay. The results show that high Vt SAR ADC saves power upto 67% as compared to low Vt SAR ADC without any penalty of delay. Other performance metrics studied are the Effective Number of Bits (ENOB) and Signal to Noise Ratio (SNR), Signal to Noise and Distortion Ratio and Spurious Free Dynamic ratio.
基于45nm CMOS技术的心电低功耗SAR ADC设计
提出了一种用于生物电位采集系统的45纳米CMOS低功耗逐次逼近寄存器模数转换器(SAR ADC)的设计。它采用高阈值电压(Vt)电池来降低功耗。设计了一个10位SAR ADC,并与低分辨率SAR ADC和正常阈值电压(Vt) ADC在功率和延迟方面进行了比较。结果表明,与低Vt SAR ADC相比,高Vt SAR ADC可节省高达67%的功率,且没有任何延迟损失。研究的其他性能指标是有效比特数(ENOB)和信噪比(SNR),信噪比和失真比以及无杂散动态比。
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