Low voltage comparator for high speed ADC

Hao Gao, P. Baltus, Qiao Meng
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引用次数: 12

Abstract

This paper presents a design of a high-speed, low-voltage, low power consumption comparator with S-R latch for High speed ADC. The comparator is the most important part in the Flash ADC, since the speed and the resolution is determined by the comparator. In this paper, we do the analysis of the traditional comparator and propose a better structure combing sense amplifier and symmetric S-R latch, which can run faster and provide more stable output signal than the traditional structure. The comparator is composed of a latch based amplifier and a S-R latch which provides stable output. There are many issues in the design of the comparator, we will discuss those design issues in this paper.
用于高速ADC的低压比较器
本文设计了一种高速ADC用S-R锁存器的高速、低压、低功耗比较器。比较器是Flash ADC中最重要的部分,因为速度和分辨率是由比较器决定的。本文对传统的比较器进行了分析,提出了一种将感测放大器和对称S-R锁存器相结合的比较器结构,该结构比传统的比较器结构运行速度更快,输出信号更稳定。比较器由一个基于锁存器的放大器和一个提供稳定输出的S-R锁存器组成。比较器的设计中存在很多问题,本文将对这些设计问题进行讨论。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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