A Cache Hardware Design for H.264 Encoder

Abstract

On the oretical basis of the inter-frame motion compensation of H.264 encoder, this paper proposed a new cache which adopted the LFU(lease frequently used) replace mechanism and a new prefetching method of reference images which have been reconstructed in H.264 encoder. We first gave its top-level framework definition, and then implemented the design using Verilog HDL. Based on the RTL coding, the design is synthesized with TSMC 90nm technology library. The result of the related experiments shows that the proposed cache can effectively save 76%~86% of the data memory bandwidth by use of the temporal correlation of data. Compared with the traditional method, the new cache architecture shows much better performance on reducing the bandwidth of accessing main storage, and presents much lower power consumption, higher hit ratio and faster access speed.