TCAD analysis of HCS degradation in LDMOS devices under AC stress conditions

Abstract

Different AC pulsed stress signals have been applied to an n-type LDMOS with shallow-trench isolation (STI). The HCS degradation curves have been measured on wafer by varying frequency and duty-cycle under a high-VDS stress for both low and high Vgs biases. The linear drain current drifts have been also investigated through TCAD predictions under AC stress conditions for the first time. A quantitative explanation of the dependence on frequency and duty cycle has been obtained using the new approach based on physical models. An extended analysis of the HCS degradation in a real switching application through a resistive load has been reported to gain an insight on the role played by the peak-HCS rates during the rising/falling edges.