Signal integrity verification using high speed monitors

Abstract

Signal integrity verification is becoming an important issue as technological process features continues to shrink and logic speed increases. Advanced technologies permit a large number of integrated devices onto chip, this characteristic enable to have high performance systems which request good levels of signal integrity. A monitoring technique for the verification of the signal integrity is presented. Two monitors are proposed in order to sense signal undershoots and overshoots at high and low logic levels respectively. The cost of the proposed verification strategy has been estimated in terms of area, extra pins and delay penalisation. Using coherent sampling, the monitors detect signal integrity violations for high speed critical signals.