Emerging MOSFET packaging technologies and their thermal evaluation

Abstract

Major MOSFET manufacturers have recently introduced innovative packaging options to achieve the next level of breakthroughs in electrical and thermal performance. Some of the innovations involve replacement of wire-bonds with solder-bumps for device interconnections in power devices and reduction in number of interfaces/paths for heat dissipation. The overall goal is to achieve small form factor MOSFET packages with significant improvements in electrical and thermal performance. This paper outlines the recent trends in MOSFET packaging and provides package-level thermal modeling results of wire-bond, strap bond, flipchip, ball-grid-array, and micro-lead-frame based packages. It also highlights the critical issues related to the processing, cost and reliability of such packages, which must be addressed before the conventional lead-frame based discrete solutions can be replaced with the new ones. Fundamental cooling mechanisms associated with different packaging technologies for MOSFETs are investigated. The impact of the internal package design on thermal performance is discussed in detail. The role of underfill materials in flip chip and BGA applications is also addressed.