Novel Target Design for Thick Resist Layers Overlay Measurement Improvement

Abstract

Metrology target quality highly impacts overlay measurement accuracy and robustness. Factors that can affect target quality include target pattern symmetry, pattern uniformity over one target, and target quality variation within wafer, wafer to wafer and lot to lot. Historically, multiple studies have revealed how metrology pattern asymmetry causes overlay measurement inaccuracy issues. Target design can address pattern asymmetry induced overlay error, to some extent, by providing a process compatible design. Metrology targets synchronously consider process compatibility, metrology system capability and target design basic rule. In some cases, the minimum design rule is constrained by process condition. Staircase loop layers of the 3D-NAND integration process are the typical case where resist thickness limits the accessible minimum CD/pitch. The required larger CD/pitch sometimes even violates the basic design rule of the metrology target. In this study, a novel target design is applied to address thick photo-resist processes. Compared to the baseline, the new target design helps address overlay error induced by pattern asymmetry, thus improving thick resist layers overlay measurement accuracy.