Test generators need to be modified to handle CMOS designs

Abstract

CMOS designs have some unique properties that prevent existing test generators from computing a test vector for a fault when one might exist. The problem lies in the premises laid out on what it takes to detect a stuck-at fault. The basic premise that states that it is required to set a line to O(1) in order to detect a stuck-at 1(0) fault, and then propagate the error to an observable point, is not a necessary and sufficient detection condition. This is due to the existence of unknown states throughout the logic. This paper shows an example to illustrate the problem; describes what it takes in order to remedy it; proposes possible enhancements to existing test generation algorithms, and outlines the risks faced in the event that no correcting steps are taken.