Self-aligned and shielded-RESURF LDMOS for dense 20 V power IC's

Abstract

A self-aligned 20 V logic-level n-channel LDMOS has been integrated in a 0.6 /spl mu/m BiCMOS process, using a LATID (large angle tilted implementation drain) boron backgate implantation combined with co-implanted arsenic as a low-ohmic link under the spacer. In addition, a shielded RESURF LDMOS is reported for use as a low-side transistor in power converters, suited for 20 V in VLSI with a single thin gate oxide. This transistor suppresses parasitic injection in the substrate and uses a buried p on buried n/sup +/ layer.