Smart Pixels Using Liquid-crystal-over-silicon

Abstract

We present preliminary characterisation of three smart plxei designs which Illustrate the application of femlectr lc l l lquld~~bver-s i l lcn technology to aystem specttlc mart plxel arrays. INTRODUCTION The hybrid Spatial Light Modulator (SLM) technology of Ferroelectric Liquid Crystal over Very Large Scale Integrated (FLCNLSI) silicon lends itself readily to the implementation of smart pixelst11. Within the UK, under the Smart and Advanced Spatial Light Modulators (SASLM) programme, we have designed prototype smart pixel arrays in FLCNLSI technology. Here, we report on three particular pixel arrays designed respectively for use in optical computing, optical image processing and optoelectronic neural networks. THE CELLULAR LoQlC PIXEL FOR OPTICAL COllllPUTlNG The pixelated optical logic plane allows the application of a superset of the normal set of Boolean logic functions to be applied simoultaneously to a bit plane of optical data. Vass[*l describes a pixel which can be programmed, by means of a set of global electrical signals, to implement any one of these logic functions; it includes connections in 2-D to eight nearest neighbours. We have designed a prototype pixel with part of this functionality and connections in l -D to two nearest neighbours. The pixel schematic is shown in Figure 1. An array of pixels has been fabricated on a test I.C. The fabrication process was 5p.m CMOS; the pixel size is 400 X 800 Fm? We describe the results of succesful testing of the pixel functionality and look at the implications for the fullf uctionality pixel. THE ISOPHOTE PIXEL FOR IMAQE PROCESSING The isophote pixel implements a variable threshold window edge enhancement functionP1. The circuit is shown in Figure 2. Two bias voltages available to all pixels determine the intensity level at which thresholding occurs. In order to determine whether a pixel lies on an edge it then computes the logic function equivalnet, POUT, to drive the FLC layer, where (The inclusion of the PlNterm ensures only one line of pixels is activated along an edge.) A 64x64 pixel array has been fabricated in 1.2pm CMOS technology. The pixel POUT = (( N @ S) + (E @ W) + (NW @ SE) + (NE @ SW)) Pi,