{"title":"Effect of Metal Gate Work Function Variation on Underlap FinFET","authors":"R. Rathore, V. Srivastava","doi":"10.1109/ISSE54558.2022.9812789","DOIUrl":null,"url":null,"abstract":"In the sub-20 nm regime, the conventional poly-Silicon material used for gate electrodes has been widely replaced by a metal gate. In this present research work, the influence of metal gate Work-Function Variability (WFV) on electrical parameters for underlap FinFET devices has been realized using the 3D electronic device simulator. In addition, the standard deviation (σ) reveals that the impact of WFV on Gate-Source/Drain (g-s/d) underlap length led to substantial fluctuations in all electrical performance parameters. This analysis suggests that the impact of WFV on performance parameters dominates in shorter g-s/d underlap length FinFET device. In addition, SRAM cell variability of three different underlap FinFET devices due to WFV has been justified. It has been concluded that WFV results in substantial performance and reliability improvement in the designed underlap FinFET devices.","PeriodicalId":413385,"journal":{"name":"2022 45th International Spring Seminar on Electronics Technology (ISSE)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 45th International Spring Seminar on Electronics Technology (ISSE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSE54558.2022.9812789","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
In the sub-20 nm regime, the conventional poly-Silicon material used for gate electrodes has been widely replaced by a metal gate. In this present research work, the influence of metal gate Work-Function Variability (WFV) on electrical parameters for underlap FinFET devices has been realized using the 3D electronic device simulator. In addition, the standard deviation (σ) reveals that the impact of WFV on Gate-Source/Drain (g-s/d) underlap length led to substantial fluctuations in all electrical performance parameters. This analysis suggests that the impact of WFV on performance parameters dominates in shorter g-s/d underlap length FinFET device. In addition, SRAM cell variability of three different underlap FinFET devices due to WFV has been justified. It has been concluded that WFV results in substantial performance and reliability improvement in the designed underlap FinFET devices.