{"title":"Reliability by Design: Avoiding Migration-Induced Failure in IC Interconnects","authors":"Susann Rothe, J. Lienig","doi":"10.1109/SBCCI55532.2022.9893237","DOIUrl":null,"url":null,"abstract":"The reliability of integrated circuits is increasingly endangered by migration-induced degradation of metal interconnects. The risk of failure due to migration is not only rising in every new technology node, it is also constraining the miniaturization of interconnect structures. In addition to DC lines, such as power delivery networks, signal and clock lines are increasingly being degraded by migration. This paper summarizes our current knowledge in avoiding migration-induced integrated-circuit failures. After introducing and discussing migration mechanisms, we focus on the growing electromigration susceptibility and the increasing influence of thermal migration. Looking forward, we review novel IC design strategies that incorporate migration constraints and mitigation measures into layout synthesis.","PeriodicalId":231587,"journal":{"name":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SBCCI55532.2022.9893237","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
The reliability of integrated circuits is increasingly endangered by migration-induced degradation of metal interconnects. The risk of failure due to migration is not only rising in every new technology node, it is also constraining the miniaturization of interconnect structures. In addition to DC lines, such as power delivery networks, signal and clock lines are increasingly being degraded by migration. This paper summarizes our current knowledge in avoiding migration-induced integrated-circuit failures. After introducing and discussing migration mechanisms, we focus on the growing electromigration susceptibility and the increasing influence of thermal migration. Looking forward, we review novel IC design strategies that incorporate migration constraints and mitigation measures into layout synthesis.