Static Design of Spin Transfer Torques Magnetic Look Up Tables for ASIC Designs

Abstract

In this paper, we propose a static approach to the design of Spin Transfer Torque Look Up Tables (STT-LUT) for integration in ASIC and investigate the sensing reliability in the proposed design in detail. The proposed design style utilizes STT-Latches that their sensing reliability is key in determining the overall reliability of the proposed static STT-LUT. The simulation results in a 10nm FinFET CMOS technology shows that the proposed static STT-LUT design exhibits up to 26% read delay reduction compared to the best dynamic STT-LUT design, and more than 2.5X reduction in sensing failure rate.