Design of a Low Power High Speed CML-Based Divide-by-5 Pre-Scaler in 180 nm Process Technology

Abstract

A power-efficient high speed MOS current mode logic (MCML)-based divide-by-5 pre-scaler is proposed in this paper. Optimized latches and XOR gates are used in order to design the proposed divide-by-5 pre-scaler. The pre-scaler is realized in 180 nm CMOS process technology and simulation results show that proposed divide-by-5 pre-scaler can faithfully work up to an operating frequency of 12.12 GHz in worst case process corner with an excellent power head performance. The maximum power dissipation of the core circuit is 1.39 mW under 1.8 V supply. The performance corresponds to figure of merit: FoM of 9.4 dB which compares favorably with the state of the art.