D. Yamazaki, S. Ide, T. Chiba, A. Hayakawa, H. Rokugawa, M. Kawai
{"title":"3R one chip CMOS IC at 156 Mbit/s","authors":"D. Yamazaki, S. Ide, T. Chiba, A. Hayakawa, H. Rokugawa, M. Kawai","doi":"10.1109/APASIC.2000.896933","DOIUrl":null,"url":null,"abstract":"A 3R one chip IC at 156 Mbit/s using PLL retiming technology has been fabricated with a 0.35 /spl mu/m CMOS. We developed a new voltage controlled oscillator (VCO) that has less deviation of free run frequency so that any adjustment is not required. We have also developed a wide dynamic range preamplifier. The use of this preamplifier and VCO realizes a 38 dB dynamic range without any requirement for adjustment of a PLL.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.2000.896933","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A 3R one chip IC at 156 Mbit/s using PLL retiming technology has been fabricated with a 0.35 /spl mu/m CMOS. We developed a new voltage controlled oscillator (VCO) that has less deviation of free run frequency so that any adjustment is not required. We have also developed a wide dynamic range preamplifier. The use of this preamplifier and VCO realizes a 38 dB dynamic range without any requirement for adjustment of a PLL.