{"title":"A Reliable 5G Stacked Power Amplifier in 45nm CMOS Technology","authors":"Zhize Ma, Saleh Mohammadi","doi":"10.1109/PAWR56957.2023.10046289","DOIUrl":null,"url":null,"abstract":"A stacked transistor microwave power amplifier (PA) operating in fifth generation (5G) broadband cellular standard is presented. The PA is implemented using stack of six advanced NMOS transistors (ADNFETs with 32 nm length in a 45nm CMOS SOI technology) and using a dynamic biasing scheme from a single power supply VDD. The operation mode can be tuned from Class-AB to Class-A by simply adjusting the VDD. Under an applied VDD of 9V (1.5V per transistor) and operating frequency of 23 GHz, the maximum measured output power reaches 21.5 dBm. At a smaller power supply of 7V, the PAE peaks at 38.4%. The PA outputs more than 20 dBm of power from 22GHz to 27 GHz. The overall performance including estimated reliability characteristics is improved compared to a similar design in the same technology but with regular NFET transistors.","PeriodicalId":207437,"journal":{"name":"2023 IEEE Topical Conference on RF/Microwave Power Amplifiers for Radio and Wireless Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 IEEE Topical Conference on RF/Microwave Power Amplifiers for Radio and Wireless Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PAWR56957.2023.10046289","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A stacked transistor microwave power amplifier (PA) operating in fifth generation (5G) broadband cellular standard is presented. The PA is implemented using stack of six advanced NMOS transistors (ADNFETs with 32 nm length in a 45nm CMOS SOI technology) and using a dynamic biasing scheme from a single power supply VDD. The operation mode can be tuned from Class-AB to Class-A by simply adjusting the VDD. Under an applied VDD of 9V (1.5V per transistor) and operating frequency of 23 GHz, the maximum measured output power reaches 21.5 dBm. At a smaller power supply of 7V, the PAE peaks at 38.4%. The PA outputs more than 20 dBm of power from 22GHz to 27 GHz. The overall performance including estimated reliability characteristics is improved compared to a similar design in the same technology but with regular NFET transistors.