A 3mW continuous-time /spl Sigma//spl Delta/-modulator for EDGE/GSM with high adjacent channel tolerance

Proceedings of the 30th European Solid-State Circuits Conference Pub Date : 2004-11-15 DOI:10.1109/ESSCIR.2004.1356648

M. Schimper, Lukas Dörrer, E. Riccio, G. Panov

引用次数: 39

Abstract

A continuous-time 4th-order multi-bit /spl Sigma//spl Delta/-modulator for GSM/EDGE is presented. By introduction of a direct feed-forward path from the input to the quantiser, high immunity to adjacent channel interferers is achieved. The dynamic range is 90 dB (>14-bit) over a 240 kHz signal bandwidth. Accurate modelling allows optimisation of excess loop delay, thus yielding a very low power consumption of 3 mW at 1.25 V supply voltage. The modulator is clocked at 26 MHz (oversampling ratio=54). It occupies 0.5 mm/sup 2/ in a 0.13 /spl mu/m CMOS technology.

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用于EDGE/GSM的3mW连续时间/spl Sigma//spl Delta/-调制器，具有高相邻信道容限

提出了一种用于GSM/EDGE的连续4阶多比特/spl Sigma//spl Delta/-调制器。通过引入从输入到量子器的直接前馈路径，实现了对相邻信道干扰的高抗扰性。动态范围为90db(>14位)，信号带宽为240khz。精确的建模可以优化多余的环路延迟，从而在1.25 V电源电压下产生非常低的3 mW功耗。调制器时钟为26 MHz(过采样比=54)。它在0.13 /spl mu/m CMOS技术中占用0.5 mm/sup / 2/。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of the 30th European Solid-State Circuits Conference

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