Configurable redundant via-aware standard cell design considering multi-via mechanism

Tsang-Chi Kan, Hung-Ming Hong, Ying-Jung Chen, S. Ruan
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引用次数: 2

Abstract

Well designed redundant via-aware standard cells (SCs) can increase the redundant via1 insertion rate in cell-based designs. However, with conventional methods, manual and visual-based check are required to locate pins and tune geometries in layouts, which can be very time consuming and unreliable. Instead, an O(NlogN) via-aware standard cell optimization algorithm is developed. The proposed method considers various redundant via configurations such as double-via and rectangle-via which effectively increase the redundant via insertion rate for both concurrent routing and post-layout optimization. As a result, the proposed scheme not only addresses the problem of a low via1 insertion rate in nanometer regimes, but also demonstrates an efficient automatic layout optimizer for designing standard cells. Compared to the conventional standard library, the proposed method saves considerable design effort and time. Experimental results reveal that the proposed method effectively improves the redundant via1 insertion rate by a total of 26.3%.
考虑多通孔机制的可配置冗余通孔感知标准单元设计
在基于细胞的设计中,设计良好的冗余过孔感知标准细胞(SCs)可以提高冗余过孔插入率。然而,使用传统方法,需要手动和基于视觉的检查来定位引脚和调整布局中的几何形状,这可能非常耗时且不可靠。取而代之的是,开发了一个O(NlogN)通过感知的标准单元优化算法。该方法考虑了双孔和矩形孔等冗余孔结构,有效地提高了冗余孔插入率,实现了并行布线和布局后优化。结果表明,该方案不仅解决了在纳米环境下低via1插入率的问题,而且为标准单元的设计提供了一种高效的自动布局优化器。与传统的标准库相比,该方法节省了大量的设计精力和时间。实验结果表明,该方法有效地将冗余via1插入率提高了26.3%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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