Generation of floating point 2D translation operators for FPGA

Abstract

This paper presents an FPGA implementation of a matrix operator for geometric two dimensional translation. The generated architecture takes advantage of the particular form of the translation matrix, ignoring the null elements. We have generated architectures for floating point operators of half, simple, double precision. In order to validate our implementations, all the operators were tested against a large number of generated unit tests. Additionally, we propose multiple architectures, targeting either performance or reduced area usage, depending on the number of functional units used.