Transition count based BIST for detecting multiple stuck-open faults in CMOS circuits

Abstract

This paper presents a BIST design suitable for detecting multiple stuck-open faults in two-level CMOS single complex cells. The test pattern generator (TPG) generates a sequence of length 2n.2/sup n/ that includes all n.2/sup n/ single-input-change (SIC) ordered test pairs for an n-input circuit under test (CUT). The signature analyzer (SA) counts the number of alternate transitions at the output. Design of the corresponding TPG and SA is straightforward.