E. Amselem, B. González, J. García, I. Aldea, M. Marrero, A. Iturri, J. del Pino, S. Khemchandani, A. Hernández
{"title":"Influence of gate geometry in integrated MOS varactors on accumulation mode for RF","authors":"E. Amselem, B. González, J. García, I. Aldea, M. Marrero, A. Iturri, J. del Pino, S. Khemchandani, A. Hernández","doi":"10.1109/SCED.2007.383997","DOIUrl":null,"url":null,"abstract":"Driven by the many applications that varactors have in RF integrated blocks, this work analyzes the influence of gate geometry (width and length) on integrated accumulation MOS varactors. For this purpose, a number of varactors have been designed and fabricated on a 0.8 mum CMOS standard technology. The most relevant parameters: quality factor, tuning range, and capacitance, are simulated and compared against measurements. Some design considerations are reported.","PeriodicalId":108254,"journal":{"name":"2007 Spanish Conference on Electron Devices","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-07-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 Spanish Conference on Electron Devices","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SCED.2007.383997","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Driven by the many applications that varactors have in RF integrated blocks, this work analyzes the influence of gate geometry (width and length) on integrated accumulation MOS varactors. For this purpose, a number of varactors have been designed and fabricated on a 0.8 mum CMOS standard technology. The most relevant parameters: quality factor, tuning range, and capacitance, are simulated and compared against measurements. Some design considerations are reported.