Design and Implementation of Reconfigurable RSA Cryptosystem

Abstract

In this paper, the hardware implementation of a reconfigurable RSA cryptosystem is presented. In order to match distinct security levels, the modified Montgomery modular multiplication algorithm is introduced into this 512/1024/2048/4096-bits RSA encryption/decryption. The huge number of register is also replaced by 5 memory blocks. As a result, our design including 5 memory blocks achieves the baud rate of 99 kb/s for 512-bit, 29 kb/s for 1024-bit, 6.8fcs/6 for 2048-bit and 1.7 kb/s for 4096-bit on Xilinx Vertex2 XC2V8000 of 6783 slices.