FPGA Implementation and Verification of Reed-Solomon (63, 47, 8) Code in SDR System

Abstract

This study used the LabView FPGA to implement the Reed-Solomon codes (R-S code) on the NI SDR PXIe-5641R FPGA module. Besides providing a detailed discussion on the encoding & decoding mechanism of R-S code, this studycompleted software simulation and hardware verification of R-S (63, 47, 8) code. When the error probability is 10^-5, the coding gain of R-S (63, 47, 8) can be up to 4dB. Compared to the R-S (31, 15, 17) code using m = 5 [8], when the E_b/N₀ is 5dB, the error probability of is 10^-2, and the error probability in thisarticle is 10^-4, indicating that the R-S (63, 47, 8) implemented in this study has better correction capacity. At same bit error probability P_b = 10^-5, the E_b/N₀ value of R-S (31, 15, 17) is 7dB, yet, the E_b/N₀value of R-S (63, 47, 8) is 5.5dB. There is a 1.5dB difference between them. When the error probability is 10_-4, the E_b/N₀ of R-S code (63, 47, 8) in this study is about 5 dB, and the R-S (63, 47, 8) [9] is 7 dB. There is a 2 dB gain for the R-S code in this study. The result of the compiling verification of the 5641R FPGA module of LabView FPGA Reed-Solomon code shows that the Total Slice use rate is 6.8% the use rate of the Slice Register is 2%, and the use rate of the S lice LUTs is 4.5%.