1 kV field plated in-situ oxide, GaN interlayer based vertical trench MOSFET (OG-FET)

Abstract

In recent years, GaN trench MOSFETs have been actively investigated to achieve low on-resistance and high breakdown voltage [1-8]. The absence of a JFET region makes the trench MOSFET a favorable device structure to reduce the on-resistance. However, poor (electron) channel mobility in GaN trench MOSFETs lead to increased channel resistance. This could potentially result in reliability issues and/or high on-resistance as a large gate bias is needed to reduce the channel resistance. In our previous works, we demonstrated a novel device design (OG-FET), where enhanced channel mobility was obtained by inserting a MOCVD-regrown GaN interlayer between the trenched structure and the in-situ gate dielectric [7, 8]. The breakdown performance of OG-FETs reported in previous work was limited due to the absence of edge termination [8]. In this work, OG-FETs were fabricated with field plate based edge termination which resulted in an enhanced breakdown from 600 V (EBR ∼ 1.5 MV/cm) to 1000 V (EBR ∼ 2 MV/cm).