ROBDD based path delay fault testable combinational circuit synthesis

Abstract

Traditional scan based transition delay fault tests can potentially miss variability induced delay faults on long interconnects. On the other hand, an ATPG may not be successful in deriving test patterns for all paths. The paper proposes a BDD based synthesis method where all the paths are testable under the path delay fault model without addition of extra inputs. Each ROBDD (Reduced-Ordered-Binary Decision Diagram) node is covered by an Invert-AND-OR sub-circuit. The paper proves that the synthesized circuit is fully testable for path delay faults, either by robust tests or validatable non-robust tests.