Ioannis Georgakopoulos, N. Hadjigeorgiou, P. Sotiriadis
{"title":"A CMOS closed loop AMR sensor architecture","authors":"Ioannis Georgakopoulos, N. Hadjigeorgiou, P. Sotiriadis","doi":"10.1109/PACET.2017.8259975","DOIUrl":null,"url":null,"abstract":"A fully analog, closed loop, signal conditioning circuit is presented for the readout of Anisotropic MagnetoResistance magnetic sensors. The architecture is based on a fully differential design, consisting of an instrumentation amplifier with chopping to achieve low output noise, followed by a transconductor. The output current of the transconductor is directly fed back to the sensor, through a dedicated on-chip inductor for magnetic field offsetting purposes, closing this way a negative feedback loop. The proposed design has been implemented and simulated in TSMC 180nm 5 V CMOS process.","PeriodicalId":171095,"journal":{"name":"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PACET.2017.8259975","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A fully analog, closed loop, signal conditioning circuit is presented for the readout of Anisotropic MagnetoResistance magnetic sensors. The architecture is based on a fully differential design, consisting of an instrumentation amplifier with chopping to achieve low output noise, followed by a transconductor. The output current of the transconductor is directly fed back to the sensor, through a dedicated on-chip inductor for magnetic field offsetting purposes, closing this way a negative feedback loop. The proposed design has been implemented and simulated in TSMC 180nm 5 V CMOS process.