Minghao Lil, Jing Tian, Xiao Hu, Yuan Cao, Zhongfeng Wang
{"title":"High-Speed and Low-Complexity Modular Reduction Design for CRYSTALS-Kyber","authors":"Minghao Lil, Jing Tian, Xiao Hu, Yuan Cao, Zhongfeng Wang","doi":"10.1109/APCCAS55924.2022.10090253","DOIUrl":null,"url":null,"abstract":"In the process of NIST post-quantum cryptography standardization, CRYSTALS-Kyber (Kyber) was selected as one of the first four candidates to be standardized for its strong security and excellent performance. Towards the computation-intensive modular reduction operation of Kyber, this paper proposes a high-speed and low-complexity modular reduction algorithm based on the signed number representation and the proposed Fast Look-Up Table (FLUT). FPGA experiment results demonstrate that our design costs nearly 25% fewer hardware resources and 25% shorter critical path than the state-of-the-art reduction design for Kyber. Moreover, the computational complexity of Inverse Number Theoretic Transform (INTT), a primary function of Kyber, is reduced using the property of our reduction algorithm.","PeriodicalId":243739,"journal":{"name":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS55924.2022.10090253","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In the process of NIST post-quantum cryptography standardization, CRYSTALS-Kyber (Kyber) was selected as one of the first four candidates to be standardized for its strong security and excellent performance. Towards the computation-intensive modular reduction operation of Kyber, this paper proposes a high-speed and low-complexity modular reduction algorithm based on the signed number representation and the proposed Fast Look-Up Table (FLUT). FPGA experiment results demonstrate that our design costs nearly 25% fewer hardware resources and 25% shorter critical path than the state-of-the-art reduction design for Kyber. Moreover, the computational complexity of Inverse Number Theoretic Transform (INTT), a primary function of Kyber, is reduced using the property of our reduction algorithm.