T. Ando, T. Tomioka, M. Nakazono, K. Atsumi, Y. Tane, J. Nakano, S. Hirata
{"title":"Single Point Outer Mad Bonding Technology For High Pin Count Ceramic PGA","authors":"T. Ando, T. Tomioka, M. Nakazono, K. Atsumi, Y. Tane, J. Nakano, S. Hirata","doi":"10.1109/IEMT.1993.639747","DOIUrl":null,"url":null,"abstract":"A new ceramic pin grid array (PGA) package for industrial computers has been developed by applying tape automated bonding (TAB) technology to one of the largest (20 plpl square) and highest pin count (820pins) application specific integrated circuits (ASIC) available in the semiconductor industry. To fabricate this package, a series of TAB processes containing inner lead bonding (ILB), cutting and forming of TAB outer leads, solder sheet mounting, outer lead bonding (OLB). die attachment and lid sealing have been developed. The key to this assembly is that a single point bonding method at room temperature has been developed for fine pitch (90 pn pitch) interconnections between TAB outer leads and electrode pads on a wavy ceramic substrate. To realize single point TAB technology, the optimum design for a tape carrier and for electrode pad patterns on a ceramic substrate has been explored, a new bonding tool has been developed, and the optimum thickness of gold, plated on the electrode pads on the ceramic substrate, has been investigated. As a result of these investigations, outer lead bond strengths exceeding 30 gf, and bonding accuracy within kt10 p have been achieved. Degradation of bond strength by thermal cycle tests was not observed.","PeriodicalId":170695,"journal":{"name":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Japan International Electronic Manufacturing Technology Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.1993.639747","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A new ceramic pin grid array (PGA) package for industrial computers has been developed by applying tape automated bonding (TAB) technology to one of the largest (20 plpl square) and highest pin count (820pins) application specific integrated circuits (ASIC) available in the semiconductor industry. To fabricate this package, a series of TAB processes containing inner lead bonding (ILB), cutting and forming of TAB outer leads, solder sheet mounting, outer lead bonding (OLB). die attachment and lid sealing have been developed. The key to this assembly is that a single point bonding method at room temperature has been developed for fine pitch (90 pn pitch) interconnections between TAB outer leads and electrode pads on a wavy ceramic substrate. To realize single point TAB technology, the optimum design for a tape carrier and for electrode pad patterns on a ceramic substrate has been explored, a new bonding tool has been developed, and the optimum thickness of gold, plated on the electrode pads on the ceramic substrate, has been investigated. As a result of these investigations, outer lead bond strengths exceeding 30 gf, and bonding accuracy within kt10 p have been achieved. Degradation of bond strength by thermal cycle tests was not observed.