Modeling split-gate flash memory cell for advanced neuromorphic computing

Abstract

Split-gate flash memory technology had recently been used in neuromorphic computation where a non-volatile memory array is designed in such a way that enables high-precision tuning of individual memory elements. This work proposes for the first time a SPICE model of the two-transistor, select gate and floating gate, of the split-gate flash memory cell, implemented in a 180 nm CMOS technology, that allows the users to set the individual memory cell to any precise analog state.