Construction of Latch Design with Complete Double Node Upset Tolerant Capability Using C-Element

Abstract

Due to VLSI downsizing and high integration, the incidence of soft error has increased. The soft error is a temporary event caused by striking of a-rays and high energy neutron radiation. Since the scale of VLSI has become smaller in recent development, it is necessary to consider the occurrence of not only single node upset (SNU) but also double node upset (DNU). The existing High-performance, Low-cost, and DNU Tolerant Latch design (HLDTL) does not completely tolerate DNU. This paper presents a DNU tolerant latch to solve this problem by adding some transistors to the HLDTL latch.