A zero aliasing built-in self test technique for delay fault testing

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99) Pub Date : 1999-11-01 DOI:10.1109/DFTVS.1999.802874

Y. Tsiatouhas, T. Haniotakis

引用次数: 8

Abstract

A zero aliasing built-in self-test (BIST) approach to detect timing related failures in VLSI circuits is proposed. The BIST scheme is based on a transition detector and is able to detect timing related failures resulting in shorter than expected as well as larger than expected delay faults.

查看原文本刊更多论文

一种用于延迟故障检测的零混叠内置自检技术

提出了一种零混叠内置自检(BIST)方法来检测VLSI电路中与时序相关的故障。BIST方案基于转换检测器，能够检测与时间相关的故障，导致比预期更短的延迟故障和比预期更大的延迟故障。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)

自引率

0.00%

发文量