An efficient zero length prefix algorithm for H.264 CAVLC decoder on TMS320C64

Abstract

In this paper, an efficient DSP-based CAVLC decoding design is proposed. CAVLC decoding module takes the lion chair of our decoder execution time due to its complexity. In order to ameliorate CAVLC implementation, two major steps are proposed: First, we take advantage of DSP architecture by organizing its appropriate internal memory buffer to design a suitable CAVLC decoder architecture. Then, a zero length prefix algorithm (ZLP) is proposed to decode the first syntax element in CAVLC, called CoeffToken. This new algorithm permits amelioration in the CAVLC time execution by up to 20% which leads to an increase in the overall decoder speed by 8 fps. The decoder has been tested with different bitstreams. According to these tests, real time decoding can be obtained on a TMS320C6416 platform running at 720MHz.