A 108-GHz Retimer Based on 1.8V QUASI-ECL MOS-HBT SiGe BiCMOS Logic

Abstract

This paper describes the first full-rate retimer operating with clock frequencies above 100- GHz. The circuit includes a digitally-controlled equalizer with over 30 dB of peaking control at 55- 60GHz, a 108-GHz flip-flop, and a DC- to-108 GHz clock amplifier. It consumes 540 mW from a 1.8V supply corresponding to an energy efficiency of 5pJ/bit. Equalization was demonstrated over 6m of coaxial cable at 40 Gb/s and 36 Gb/s with full-rate, 2x, and 3x oversampling clocks at 80 GHz and 108 GHz, respectively, and at 75 Gb/s with 75-GHz clock between two probe stations using wafer probes and a 3-m long coaxial cable.