Elpida Kaskouta, Themis Kamilaris, R. Sotner, J. Jerabek, C. Psychalinos
{"title":"Single- Input Multiple-Output and Multiple-Input Single-Output Fractional-Order Filter Designs","authors":"Elpida Kaskouta, Themis Kamilaris, R. Sotner, J. Jerabek, C. Psychalinos","doi":"10.1109/TSP.2018.8441348","DOIUrl":null,"url":null,"abstract":"Novel single-input multiple-output and multiple-input single-output fractional-order filter topologies are presented in this paper. They are constructed from two fractional-order integrators with appropriate feedback and feed-forward paths, as well as from summation stages. The employed active cells are Operational Transconductance Amplifiers, providing the capability for electronic tuning of the realized time-constants, while the required fractional-order capacitors are approximated by appropriately configured RC networks. The provided simulation results, obtained using the Analog Design Environment of the Cadence software and the Design Kit from Austrian Mikro Systems1 0.35μ m CMOS process, confirm the correct operation of the proposed topologies.","PeriodicalId":383018,"journal":{"name":"2018 41st International Conference on Telecommunications and Signal Processing (TSP)","volume":"411 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 41st International Conference on Telecommunications and Signal Processing (TSP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TSP.2018.8441348","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
Novel single-input multiple-output and multiple-input single-output fractional-order filter topologies are presented in this paper. They are constructed from two fractional-order integrators with appropriate feedback and feed-forward paths, as well as from summation stages. The employed active cells are Operational Transconductance Amplifiers, providing the capability for electronic tuning of the realized time-constants, while the required fractional-order capacitors are approximated by appropriately configured RC networks. The provided simulation results, obtained using the Analog Design Environment of the Cadence software and the Design Kit from Austrian Mikro Systems1 0.35μ m CMOS process, confirm the correct operation of the proposed topologies.
提出了一种新颖的单输入多输出和多输入单输出分数阶滤波器拓扑结构。它们由两个具有适当反馈和前馈路径的分数阶积分器以及求和阶段构造而成。所采用的有源单元是操作跨导放大器,提供实现时间常数的电子调谐能力,而所需的分数阶电容器由适当配置的RC网络近似。利用Cadence软件的模拟设计环境和奥地利Mikro Systems1 0.35μ m CMOS工艺的设计套件进行仿真,验证了所提出的拓扑结构的正确运行。