A Fast-Lock Technique for Digital Sub-Sampling Fractional-N Phase-Locked-Loops

Abstract

In digital sub-sampling (SS) phase-locked-loops (PLLs), to lock the frequency, phase frequency detectors (PFDs) with large dead-zones and a digitally-controlled-oscillator with multi-bank are usually employed following a long transient. In this paper, we propose a technique assisting fast-lock for digital fractional-N SS-PLLs via the PFD with small dead-zone. This technique is based on the use of a low reference frequency for the sub-sampling loop, breaking interference between this loop and frequency-locked-loop (FLL) in phase-lock. Comparison between simulated results of the SS-PLL employing the proposed technique and of the one employing a common reference frequency for both the FLL and the sub-sampling loop show that, with the novel technique, the transient time is much shortened while the output phase noise performance is maintained.