A 4GHz-bandwidth op-amp-free track-and-hold and 6-bit flash ADC in 45nm SOI CMOS

Abstract

A 2GS/s 6-bit flash sub-ADC with an op-amp free track-and-hold (T&H) for use in an 8GS/s 4-way time-interleaved ADC was implemented in 45nm SOI CMOS. The T&H utilizes a passive charge sharing technique and achieves a 4GHz input bandwidth at 2GS/s clock rate without an op-amp. The flash sub-ADC consumes 74mW at 2GS/s and occupies an area of 0.2mm2. The measured INL and DNL are -0.9/1.0LSB and -1.35/0.9LSB, respectively. The sub-ADC SNDR is 33.9dB at 2GS/s with a 125MHz input and 30.6dB with a 4GHz input.