Implementation of Split-Radix Fast Fourier Transform on FPGA

Abstract

Nowadays, portable systems are developed especially for signal processing, where the principal challenge is to find circuits with less area and power consumption. One of the most powerful tools in the area of Signal Processing is the Fast Fourier Transform (FFT). Many algorithms have been developed to improve its computation time; one of them is the Split Radix Fast Fourier Transform (SRFFT) which reduces the number of complex computation. Therefore, a new architecture is proposed to compute the SRFFT. Although the runtime of this design is high, it has some important profits like a flexible number of inputs N=2P; few resources required such as combinational functions, logic registers and memory.