Performance Analysis of Low Power Null Convention Logic Units with Power Cutoff

Abstract

Null convention logic units are the most important logic units in asynchronous circuits. This paper proposes a new realization of null convention logic unit based on semi-static threshold gates. Through adding a cutoff transistor into the pull-up path, the leakage current can be greatly decreased, which can resolve the issue of leakage current increment in deep submicron technology. Comparisons are made on delay, area, power consumption as well as working speed with the conventional logic units. One bit asynchronous adder and basic gates are realized based on the proposed null convention logic unit and comparisons are made on performance and power consumption. Results have shown that the new null convention logic unit has significant decrements in dynamic and static power consumption. Dynamic power consumption of TH33 gate has decreased by 13.6%, and 72.9% to the static power consumption. The newly design proposal can satisfy the requirement of low power asynchronous design.