ESD protection in deep submicron CMOS technology -- Does the transient matter?

Abstract

Common ESD protection devices have a snap-back characteristic similar to a siliconcontrol-rectifier. The transient voltage required to trigger these devices usually is not an important design criterion as long as it is not too high. We show that when gate-oxide is thin, this voltage transient creates far more defects in the gate-oxide than the main ESD event clamped at the holding voltage. Due to difficulty in measurement, this oxide reliability degradation can lead to chip failure but not show up in simulated ESD test.