A Galois Field Based Logic Synthesis Approach with Testability

J. Mathew, H. Rahaman, Ashutosh Kumar Singh, A. Jabir, D. Pradhan
{"title":"A Galois Field Based Logic Synthesis Approach with Testability","authors":"J. Mathew, H. Rahaman, Ashutosh Kumar Singh, A. Jabir, D. Pradhan","doi":"10.1109/VLSI.2008.88","DOIUrl":null,"url":null,"abstract":"In deep-submicron VLSI, efficient circuit testability is one of the most demanding requirements. Efficient testable logic synthesis is one way to tackle the problem. To this end, this paper introduces a new fast efficient graph-based decomposition technique for Boolean functions in finite fields, which utilizes the data structure of the multiple-output decision diagrams (MODD). In particular, the proposed technique is based on finite fields and can decompose any N valued arbitrary function F into N distinct sets conjunctively and N-l distinct sets disjunctively. The proposed technique is capable of generating testable circuits. The experimental results show that the proposed method is more economical in terms of literal count compared to existing approaches. Furthermore, we have shown that the basic block can be tested with eight test vectors.","PeriodicalId":143886,"journal":{"name":"21st International Conference on VLSI Design (VLSID 2008)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2008-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"21st International Conference on VLSI Design (VLSID 2008)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI.2008.88","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

Abstract

In deep-submicron VLSI, efficient circuit testability is one of the most demanding requirements. Efficient testable logic synthesis is one way to tackle the problem. To this end, this paper introduces a new fast efficient graph-based decomposition technique for Boolean functions in finite fields, which utilizes the data structure of the multiple-output decision diagrams (MODD). In particular, the proposed technique is based on finite fields and can decompose any N valued arbitrary function F into N distinct sets conjunctively and N-l distinct sets disjunctively. The proposed technique is capable of generating testable circuits. The experimental results show that the proposed method is more economical in terms of literal count compared to existing approaches. Furthermore, we have shown that the basic block can be tested with eight test vectors.
一种具有可测试性的基于伽罗瓦场的逻辑综合方法
在深亚微米VLSI中,高效的电路可测试性是最苛刻的要求之一。有效的可测试逻辑综合是解决这个问题的一种方法。为此,本文引入了一种新的基于图的有限域布尔函数快速高效分解技术,该技术利用多输出决策图(MODD)的数据结构。该方法基于有限域,可将任意N值函数F分解为N个合取的不同集和N- 1个析取的不同集。所提出的技术能够产生可测试的电路。实验结果表明,与现有方法相比,该方法在文字计数方面更加经济。此外,我们还证明了基本块可以用八个测试向量进行测试。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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