Advances in industrial practices for optimal performance/reliability/power trade-off in commercial high-performance microprocessors for wireless applications

Abstract

This paper deals with the challenge of optimizing the performance/reliability/power trade-off in commercial high-performance microprocessors for wireless applications in advanced CMOS nodes. Both the increased impact of electrical reliability degradation and an increased thermal runaway risk require a dedicated approach combining product engineering and high-level modeling approach to achieve optimal reliability guardband determination even in the case of numerous, discrete V-F operating modes and their related mission profiles.