A Mixed Solder Grid Array And Peripheral Leaded Mcm Package

Abstract

We have developed a unique low cost Multichip Module (MCM) piickage to house a 40MHz Digital Signal Processor Static RAM chipset. A collaborative design and prototype effort was undertaken between hlCC and Motorola to design, procure, assemble, and test these modules. Our design constraint w'as to merge a state-of-the-art high density interconnect subsitrate with conventional chip assembly techniques while meeting a pre-specified cost goal. The package concept is that of an MCM-L substrate with more than one chip, where the chips are connected to the substrate by means of conventional gold wire bonding and the part is overmolded. A mix of solder balls and peripheral leads are used to interface to the package. The mix of package connectorization alpproaches is used to increase the routing resources, decouple the signal and power / ground distribution, and provide good thermal coupling between the package and the next level board. Issues such as board layout, component design and fabricaition, board assembly, and first order cost models are discussad. Traditionally (only one die is placed in a package for surface or through-hole mounting. Few chip packaging involves the placement of more than one die into an enclosed package which can be handled and mounted using traditional printed circuit bOiUd assembly technologies. A few chip package, in this context, is defined as a Multichip Module (MCM) that conforms to an existing standard single chip package footprint and form factor and contains more than one chip. As the VO of chips going into conventional Quad Flat Packages (QFPs) and Pin Grid Arrays @GAS) have increased, the package size has grown extensively. In a commercial 160 lead QFP, the ratio of the silicon area to the package area is 10 mm square/28 mm square, or S1396. Besides reducing system size and cost, few chip packages allow improvements in electrical performance by grouping performance sensitive portions of a syswm into MCMs while not penalizing system assembly. Few chip packages also offer the potential for improved testability over solutions which do not include single chip packagles (i.e. MCMs) 111. There are a number of approaches which have been used to form few chip packages [2-91. In some cases small printed circuit boards containing multiple chips have been attached to the die attach pad of a leadframe for packaging into a single chip package [4]. Similarly, silicon-on-silicon modules conraining multiple chips have been placed inside plastic chip carriers [5 ] , and intoceramic PGA's [61. Companies such as Ibiden. ISI, Accurel, Hestia, TI, ATBrT, and Motorola have been working on various approaches to few chip packages for a number of years. The substrates used to interconnect the components vary from a thin film MCM in the case of AT&T Polyhic package [61 to fine line PCB's [8,91. Our approach was to explore the lower cost more simplified process that simultaneously allowed use of multiple viable vendors for key process components and could be easily transferred to manufacturing. This paper is organized as follows: first the test vehicle is described, then characteristics of the joint development efforts and rationale for the program is explained. Then we review the assembly process flow and features of design. Preliminary test data and key areas of concerns are discussed next. A simple first order cost analysis based on available data from multiple vendors for each component is reviewed. Finally, a summary of project development is reported. A few chip package based on the Motorola,M56002 Qigital Signal Processor (DSP) chip set was designed. The design consists of four ICs and five capacitors. There is a total of 270 wire bond connections on the module, and 121 off-module peripheral connections. There is a 14x14 array of solder balls on the bottom layer, 60 of which are used for power and ground connections to the next level board. The module can operate up to 60MHz with nano-second edge rates present on the board and may generate up to 4 W. The key driver in this exercise is to analyze the impact on size, performance, and cost of a unique design concept where a peripheral quad-flat-package leadframe is integrated into Motorola's overmolded pad array camer (OMPAC) [lo] (Figure 1). The design criteria set forth for this chipset was an aggressive, yet manufacturable low cost board technology which strikes a balance between size and manufacturability. The core of the interconnect is a 4-layer 30x30 mm fine line printed circuit board (PCB). In this collaborative effort, Motorola provided the chipset and MCC designed and procured the board and handled the MCM assembly. MCC developed a series of MCM-L enabling assembly processes such as direct frame attach, component attach, and wire bonding. Motorola completed the packaging process with overmolding and solder ball attachment. The functional and life testing is performed at Motorola and the test results are shared with MCC and its project participants. Rationale for mixing solder bal Is andpen 'uheral leads A major trend for IC packaging is size reduction for many applications, especially for portable products. Array connction technology such as pin grid array and solder grid anay packages are efficient with respect to the number of interconnects per unit area. Our unique configuration adds many leads to the existing periphery of the array package. There is little size penalty for the additional number of usable 40s with this concept The trend for portable electronic products is to operate at 3.3V or lower voltages. Our unique configuration provides the IC, the package, and the system designers new options to balance the tradeoffs between size. thermal, and electrical performance. There are some design advantages which optimize the system performance as well. The solder ball interconnects. locmxI on the back of the package. are multi-functional. In this case they are used, with thermal vias located in both the package and system substrate, to provide many low resistance thermal paths. The electrical parasitics of this array are generally much lower than the peripheral leads. Here again the designers can optimize the elecuical performance by using the low resistance and low inductance of solder ball interconnects for functions such as power / ground and clock lines. The peripheral leads are available for the remaining functional I/O signals. A third advantage of our unique concept is the added mechanical robustness with the cotxoination of interconnects. Mismatch of the coefficient of thermal expansion between the IC package and the system substrate is minimized, thus improving mechanical life performance. In summary, this design technique offers a chance to optimize the packaging solution for signal dismbution, power 1 ground distribution, and cooling. The DSP is a 0 . 8 ~ CMOS chip with 132 UO, with an area of 0.317" x 0.313" that generates up to 1W. It interfaces with three Motorola 0 . 6 5 ~ M6206 32Kx8 SRAMs. Each SRAM has 46 YO, an area of 0.406" x 0,144" and generates up to 1W. The module can operate up to 60MHz with nanosecond edge rates present on theboar& The DSP56002 is a 20 MIPS processor that is a member of Motorola's family of HCMOS, low power, 24-bit general purpose Digital Signal Processors. This device is essentially a high-speed DSP which includes two new features: On-Chip Emulation (OnCE)TM and a phase locked loop (PLL). The OnCE allows simple, inexpensive, and speed independent access to the internal registers for debugging the MCM test code. The PLL allows. the DSP56002 MCM to use almost any available clock for full speed Dperation and supplies an output clock synchronized to the internal DSP clock. Other key DSP56002 features include three execution units that operate in parallel the data ALU, address generation unit, and program control unit in addition to a memory expansion port, two 256-word data RAMs, two pre-programmed data ROMs, a programmable RAM, a Serial Communication Interface (SCI), Host Interface, and Synchronous Serial Interface (SSI). The high performance of the DSP56000 family is well known in communication, high-speed control, numeric processing, computer, and audio applications. The DSP MCM speed performance is initially a 40 MHz clock rate with higher clock speeds available in the future. Because the 1/0 all switch in the sub-two-nanosecond time, this processor was chosen to test the electrical capabilities of the MCM