Formal sizing rules of CMOS circuits

Abstract

Presents a local strategy for sizing CMOS circuits. The authors show how the explicit definition of delays can be used to define delay/area optimal sizing rules. Examples are given for sizing irregular inverter arrays, NAND gates and adder cells, starting from an initial electrical netlist and ending with the fully automatically generated layout. Direct comparisons of speed/area performances are given for a linear matrix style layout implementation.<>