High density SRAM bitcell architecture in 3D sequential CoolCube™ 14nm technology

Abstract

In this paper, we present a high density 4T SRAM bitcell designed with 3D sequential CoolCube™ technology based on FD-SOI transistors in 14nm node. An in-house SPICE characterization testbench is used to optimize the critical operations (read and hold) of a 4T SRAM bitcell through post layout simulations. Results show that the proposed 3D 4T Bitcell offers 30% footprint reduction compared to the planar 6T SRAM bitcell in 14nm FD-SOI technology.