Single-V/sub DD/ and single-V/sub T/ super-drowsy techniques for low-leakage high-performance instruction caches

N. Kim, K. Flautner, D. Blaauw, T. Mudge
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引用次数: 44

Abstract

In this paper, we present a circuit technique that supports a super-drowsy mode with a single-V/sub DD/. In addition, we perform a detailed working set analysis for various cache line update policies for placing lines in a drowsy state. The analysis presents a policy for an instruction cache and shows it is as good as or better than more complex schemes proposed in the past. Furthermore, as air alternative to using high-threshold devices to reduce the bitline leakage through access transistors in drowsy caches, we propose a gated bitline precharge technique. A single threshold process is now sufficient. The gated precharge employs a simple but effective predictor that almost completely hides any performance loss incurred by the transitions between sub-banks. A 64-entry predictor with 3 bits per entry reduces the run-time increase by 78%, which is as effective as previous proposals that used content addressable predictors with 40 bits per entry. Overall, the combination of the proposed techniques reduces the leakage power by 72% with negligible (0.4%) run-time increase.
用于低泄漏高性能指令缓存的单v /sub DD/和单v /sub T/超级嗜睡技术
在本文中,我们提出了一种支持单v /sub DD/超嗜睡模式的电路技术。此外,我们对用于将行置于困倦状态的各种缓存行更新策略执行详细的工作集分析。分析提出了一种指令缓存策略,并表明它与过去提出的更复杂的方案一样好,甚至更好。此外,作为使用高阈值器件来减少休眠缓存中访问晶体管的位线泄漏的空气替代方案,我们提出了一种门控位线预充电技术。现在,单个阈值处理就足够了。门控预充采用了一个简单但有效的预测器,几乎完全隐藏了子银行之间转换所导致的任何性能损失。64项预测器,每个条目3位,减少了78%的运行时间增长,这与以前使用每个条目40位的内容可寻址预测器的建议一样有效。总的来说,所提出的技术组合减少了72%的泄漏功率,而运行时间的增加可以忽略不计(0.4%)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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