Propagation delay dependence on channel fins and geometry aspect ratio of 16-nm multi-gate MOSFET inverter

Abstract

Fin-type vertical channel Field Effect Transistors (FETs) are promising alternatives for the sub-32-nm CMOS technologies. This work investigates the impact of fin number and structure on Vth degradation and transient behavior of devices and circuits. Vertical channel transistors with different fin aspect ratio (AR = the fin height / the effective fin width) are explored. The multi-fin FinFETs (AR = 2) has a better channel controllability and a larger device width than tri-gate (AR = 1) and quasi-planar (AR = 0.5) MOSFETs. Though the increase of fin aspect ratio provides larger effective device width and driving current, the gate capacitance is increased also and limits the intrinsic device gate delay. The transient characteristics of single-/multi-fin inverter circuits are then examined by adding the load capacitance of circuits (1 and 10 fF). The added capacitance dominates the overall load capacitance and reduces the impact of the device intrinsic capacitance. The delay time is therefore dominated by the driving current of transistor and the multi-fin circuits performed a smaller delay time than the single-fin circuits. Additionally, the large driving capability of FinFET implies the less impact of load capacitance variation resulted from process variation. The multi-fin FinFETs exhibit better channel controllability against intrinsic parameter variation of active transistor and also mitigate the impact of process variation induced load capacitance variation of interconnect.