Extracting of substrate network resistances in RF CMOS transistors

Abstract

Substrate network resistances are analyzed and extracted for multi-finger MOS transistors used in RF applications. The commonly used model for MOS transistors in RF applications mainly consists of a substrate resistance network having three resistors. A typical horse-shoe CMOS transistor is laid out and all substrate resistances are extracted from I-V characteristics. Device and process simulation results for 0.25 /spl mu/m CMOS technology show that the horse-shoe structure decreases the parasitic substrate resistance by 27%. Additionally, we show that the results obtained by the traditional approximation method deviated about 31% from the exact results. Furthermore, with the proposed method, the substrate resistance values can be exactly extracted.