Patching circuit design based on reserved CLBs

Abstract

The new approach to patching circuit design that allows masking any logical gate faults of combinational circuit (combinational part of sequential circuit) C is considered. It is supposed that only one gate may be fault. There are reserved Configurable Logic Blocks (CLBs) based on Look Up Tables (LUTs) that may mask a gate fault being included into the circuit through Multiplexer (MUX). The suggested approach to patching circuit design in contrast with currently in use allows keeping performance of a fault free circuit. It is suggested to include MUXs in those internal poles of circuit C that may have hard detectable faults. Experimental results showed that masking LUT based circuits are as a rule, rather simple.