Sensitivity of a 20-GS/s InP DHBT latched comparator

2010 22nd International Conference on Indium Phosphide and Related Materials (IPRM) Pub Date : 2010-07-23 DOI:10.1109/ICIPRM.2010.5515962

S. Kraus, R. Makon, I. Kallfass, R. Driad, M. Moyal, D. Ritter

引用次数: 1

Abstract

We present simulations and measurements of the sensitivity of a master-slave emitter-coupled logic (ECL) latched comparator implemented in an InP/GaInAs DHBT technology. The circuit exhibited simulated and experimental sensitivities of 11.5 mV and 17 mV, respectively, at a clock rate of 20 GHz, with no preamplifier

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20-GS/s InP DHBT锁存比较器的灵敏度

我们提出了在InP/GaInAs DHBT技术中实现的主从发射器耦合逻辑(ECL)锁存比较器的灵敏度模拟和测量。该电路在无前置放大器的情况下，时钟频率为20 GHz，模拟灵敏度为11.5 mV，实验灵敏度为17 mV

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2010 22nd International Conference on Indium Phosphide and Related Materials (IPRM)

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